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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P316A
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75P316A is a product of the PD75316 with on-chip ROM having been replaced with the one-time PROM or EPROM. It is most suitable for test production during system development and for production in small amounts since it can operate under the same supply voltage as mask products. The one-time PROM product is capable of writing only once and is effective for production of many kinds of sets in small quantities and early startup. The EPROM product allows program writing and rewriting, and is therefore suitable for system evaluation. The on-chip RAM has twice the capacity of the PD75316/75P316, enabling large amounts of data to be processed. Details of functions are described in the User's Manual shown below. Be sure to read in design. PD75308 User's Manual : IEM-5016
FEATURES
* Compatible (excluding mask option) with the mask products * Memory capacity * Program memory (PROM) : 16256 x 8 bits * Data memory (RAM) : 1024 x 4 bits * Low-voltage operation capability: 2.7 to 6.0 V
ORDERING INFORMATION
Ordering Code PD75P316AGF-3B9 PD75P316AK Package 80-pin plastic QFP (14 x 20 mm) 80-pin ceramic WQFN (LCC with window) On-Chip ROM One-time PROM EPROM
QUALITY GRADE
Ordering Code PD75P316AGF-3B9 PD75P316AK Package 80-pin plastic QFP (14 x 20 mm) 80-pin ceramic WQFN (LCC with window) Quality Grade Standard Standard
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
In descriptions common to one-time PROM products and EPROM products in this document, the term "PROM" is used.
The information in this document is subject to change without notice.
Document No. IC-2524A (O. D. No. IC-7950B) Date Published October 1993 P Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1992
PD75P316A
PIN CONFIGURATION (Top View)
S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7 COM0 COM1 COM2 COM3
80797877767574737271706968676665 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25262728293031323334353637383940
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5
S11
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 X2 X1 VPP XT2 XT1 VDD P33 (MD3) P32 (MD2) P31/SYNC (MD1) P30/LCDCL (MD0) P23/BUZ P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1
2
VLC0 VLC1 VLC2 P40 P41 P42 P43 VSS P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0
PD75P316AGF PD75P316AK
BIAS
m
BLOCK DIAGRAM
BASIC INTERVAL TIMER INTBT PROGRAM COUNTER (14) SP(8) CY
PORT0
4
P00-P03
PORT1
4
P10-P13
TI0/P13 PTO0/P20
TIMER/EVENT COUNTER #0 INTT0
ALU
PORT2
4
P20-P23 P30-P33 /MD0-MD3 P40-P43
BANK
PORT3
4
PORT4 BUZ/P23 WATCH TIMER PROGRAM MEMORY (PROM) SI/SB1/P03 SO/SB0/P02 SCK/P01 SERIAL BUS INTERFACE INTCSI 16256 x 8 BITS DECODE AND CONTROL GENERAL REG. PORT5
4
4
P50-P53
INTW
fLCD
m
INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 -KR7/P73
PORT6 DATA MEMORY (RAM) 1024 x 4 BITS
4
P60-P63
PORT7
4
P70-P73
24 8
INTERRUPT CONTROL LCD CONTROLLER /DRIVER CPU CLOCK fLCD
S0-S23 S24/BP0 -S31/BP7 COM0-COM3 VLC0-VLC2 BIAS LCDCL/P30 SYNC/P31
4 3
fX / 2
BIT SEQ. BUFFER (16)
N
SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT DIVIDER SUB MAIN CONTROL CONTROL PCL/P22 XT1 XT2 X1 X2
PD75P316A
VPP VDD VSS RESET
3
PD75P316A
CONTENTS 1. PIN FUNCTIONS ......................................................................................................................................... 5
1.1 1.2 1.3 1.4 PORT PINS ........................................................................................................................................................... 5 OTHER PINS ......................................................................................................................................................... 7 PIN INPUT/OUTPUT CIRCUITS ......................................................................................................................... 9 CAUTION ON USING P00/INT4 PIN AND RESET PIN .................................................................................. 11
5 2. 3. 4.
DIFFERENCES BETWEEN PRODUCTS IN SERIES ............................................................................... 11 DATA MEMORY (RAM) ............................................................................................................................ 13 PROGRAM MEMORY WRITE AND VERIFY ........................................................................................... 15
4.1 4.2 4.3 4.4 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ....................................................................... 15 PROGRAM MEMORY WRITING PROCEDURE ............................................................................................... 16 PROGRAM MEMORY READING PROCEDURE ............................................................................................... 17 ERASURE METHOD .......................................................................................................................................... 18
5. 6. 7.
ELECTRICAL SPECIFICATIONS ............................................................................................................... 19 PACKAGE INFORMATION ....................................................................................................................... 35 RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 37
APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 38 5 APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 39
4
PD75P316A
1. PIN FUNCTIONS
1.1 PORT PINS (1/2)
Pin Name P00 P01 P02 P03 P10 P11 Input P12 P13 P20 P21 Input/output P22 P23 P30 *2 P31 *2 Input/output P32 *2 P33 *2 MD2 MD3 N-ch open-drain 4-bit input/output port (PORT 4). Data input/output pins for program memory (PROM) write/verify (low-order 4 bits). PCL BUZ LCDCL MD0 SYNC MD1 Programmable 4-bit input/output port (PORT3) Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit. x INT2 TI0 PTO0 -- 4-bit input/output port (PORT2) Internal pull-up resistor specification by software is possible as a 4-bit unit. x Input/Output Input Input/output Input/output Input/output DualFunction Pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1 With noise elimination circuit 4-bit input port (PORT1) Internal pull-up resistor specification by software is possible as a 4-bit unit. x 4-bit input port (PORT0) Internal pull-up resistor specification by software is possible for P01 to P03 as a 3-bit unit. x Function 8-Bit I/O Afer Reset I/O Circuit Type*1 B F -A Input F -B M-C
Input
B -C
Input
E-B
Input
E-B
P40 to P43*2
Input/output
--
High impedance
M-A
P50 to P53 *2
Input/output
--
N-ch open-drain 4-bit input/output port (PORT 5) Data input/output pins for program memory (PROM) write/verify (high-order 4 bits).
High impedance
M-A
P60 P61 P62 P63 P70 P71 P72 P73 Input/output Input/output
KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 4-bit input/output port (PORT7). Internal pull-up resistor specification by software is possible as a 4-bit unit. Programmable 4-bit input/output port (PORT6). Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit.
Input
F -A
Input
F -A
*
1. : Indicates a Schmitt-triggered input. 2 . Direct LED drive capability.
5
PD75P316A
1.1
PORT PINS (2/2)
Pin Name BP0 BP1
Input/Output
DualFunction Pin S24 S25
Function
8-Bit I/O
After Reset
I/O Circuit TYPE
Output BP2 BP3 BP4 BP5 Output BP6 BP7 S30 S31 S26 S27 S28 S29 1-bit output port (BIT PORT) Dual-function as segment output pins. x
*
G-C
*
For BP0 to BP7, VLC1 is selected as the input source. The output level depends on BP0 to BP7 and the VLC1 external circuit, however.
6
PD75P316A
1.2
OTHER PINS
Pin Name TI0 PTO0 PCL BUZ SCK SO/SB0
Input/Output Input output Input/output Input/output Input/output Input/output
DualFunction Pin P13 P20 P22 P23 P01 P02
Function External event pulse input pin for timer/event counter. Timer/event counter output pin Clock output pin Fixed frequency output pin (for buzzer or system clock trimming) Serial clock input/output pin Serial data output pin Serial bus input/output pin Serial data input pin Serial bus input/output pin Edge-detected vectored interrupt input pin (rising or falling edge detection). Edge-detected vectored interrupt input pin (detection edge selectable) Edge-detected testable input pin (rising edge detection) Testable Input/output pins (parallel falling edge detection) Testable Input/output pins (parallel falling edge detection) Segment signal output pins Segment signal output pins Common signal output pins LCD drive power supply pins External split cutting output pin External extension driver drive clock output pin External extension driver synchronization clock output pin
After Reset -- Input Input Input Input Input
I/O Circuit Type *1 B -C E-B E-B E-B F -A F -B M-C
SI/SB1
Input/output
P03
Input
INT4 INT0
Input
P00 P10 P11
--
B
Input INT1 INT2 KR0 to KR3 KR4 to KR7 S0 to S23 S24 to S31 COM0 to COM3 VLC0 to VLC2 BIAS LCDCL*2 SYNC*2 Input Input/output Input/output Output Output Output -- -- Input/output Input/output
-- -- Input Input *3 *3 *3 -- High impedance Input Input
B -C
P12 P60 to P63 P70 to P73 -- BP0 to 7 -- -- -- P30 P31
B -C F -A F -A G-A G-C G-B -- -- E-B E-B
X1, X2
Input
--
Main system clock oscillation crystal/ceramic connection pins. When an external clock is used, the clock is input to X1 and the inverted clock to X2. Subsystem clock oscillation crystal connection pins When an external clock is used, the clock is input to XT1 and the inverted clock to XT2. XT1 can be used as a 1-bit input (test) pin. System reset input pin (low-level active). Mode selection pin for program memory (PROM) write/ verify. Program voltage application pin for program memory (PROM) write/verify . Connected to VDD in normal operation. Applies +12.5 V in program memory write/verify. Positive power supply pin GND potential pin
--
--
XT1, XT2
Input
--
--
--
RESET MD0 to MD3
Input Input/output
-- P30 to P33
-- Input
B E-B
VPP
--
--
--
--
VDD VSS
-- --
-- --
-- --
-- --
7
PD75P316A
*
1. : Indicates a Schmitt-triggered input. 2. Pins provided for future system expansion. Currently used only as pins 30 and 31. 3. VLCX shown below can be selected for display outputs. S0 to S31: VLC1, COM0 to COM2: VLC2 , COM3: VLC0 However, display output levels depend on the display output and VLCX external circuit.
8
PD75P316A
1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits of each pin of the PD75P316A are shown by in abbreviated form. TYPE A (For TYPE E-B)
VDD data P-ch IN N-ch output disable N-ch P-ch OUT
TYPE D (For TYPE E-B, F-A)
VDD
CMOS standard input buffer TYPE B
Push-pull output that can be made high-impedance output (P-ch and N-ch OFF) TYPE E-B
VDD P.U.R. P.U.R. enable P-ch
IN
data Type D output disable
IN/OUT
Type A
P.U.R.:Pull-Up Resistor
Schmitt trigger input with hysteresis characteristic
TYPE B-C
TYPE F-A
VDD
VDD
P.U.R.
P.U.R. P.U.R. enable
data
P.U.R. enable
P-ch
P-ch
IN/OUT Type D
output disable
IN
P.U.R. : Pull-Up Resistor
Type B
Schmitt trigger input with hysteresis characteristic
P.U.R.:Pull-Up Resistor
9
PD75P316A
TYPE F-B
VDD P.U.R. P.U.R. enable P-ch VDD P-ch
TYPE G-C
VDD P-ch VLC0 VLC1 P-ch SEG data/Bit Port data VLC2 N-ch OUT N-ch
output disable (P) data output disable output disable (N)
IN/OUT
N-ch
P.U.R.:Pull-Up Resistor
TYPE G-A
TYPE M-A
IN/OUT
VLC0 P-ch VLC1 P-ch SEG data N-ch VLC2 N-ch OUT
data output disable
N-ch (+10 V Withstand Voltage)
Middle-High Voltage Input Buffer (+10 V Withstand Voltage)
TYPE G-B
TYPE M-C
VDD
VLC0 VLC1
P-ch
P.U.R. enable
P.U.R. P-ch IN/OUT
P-ch N-ch
OUT COM data N-ch VLC2 N-ch P-ch
data output disable
N-ch
P.U.R.:Pull-Up Resistor
10
PD75P316A
1.4 CAUTION ON USING P00/INT4 PIN AND RESET PIN The P00/INT4 and RESET pins have a test mode setting function (IC test only) which tests internal operations of the PD75P316A in addition to those functions given in 1.1 and 1.2. The test mode is set when voltage greater than VDD is applied to either pin. Therefore, even during normal operation, the test mode is engaged when noise greater than VDD is added, thus causing interference with normal operation. For example, this problem may occure if the P00/INT4 and RESET pins wiring is too long, causing line noise. To avoid this, try to suppress line noise in wiring. If line noise is still high, try elimminating the noise using the exterior add-on components shown in the Figures below. * Connect a diode with low VF between the VDD and the pin. * Connect a condenser between the VDD and the pin.
5
VDD
VDD
Diode with Small VF
VDD P00/INT4, RESET
VDD P00/INT4, RESET
2. DIFFERENCES BETWEEN PRODUCTS IN SERIES
The PD75P316A is a product of the PD75316 with on-chip mask ROM having been replaced with the one-time PROM or EPROM. If you use PROM for debugging the applied system or trial manufacturing, and proceed to use masked ROM products for mass production, do so only with a full understanding of their differences beforehand. Also, PD75P316A functions are an extension of those of the PD75P316. Table 2-1 shows the differences between the series products. All products have the same functions except as indicated in this table. For the details of the CPU functions and the built-in hardware, please refer to the PD75308 User's Manual (IEM5016).
11
12 Table 2-1 Differences between Products in Series
Product Name Comparison Item ROM(x 8 bits) RAM(x 4 bits) Mask option No. 50 to 53 Pin connection No. 57
PD75304/75306/75308
Mask ROM 4K/6K/8K
PD75312/75316
Mask ROM 12K/16K 512
PD75304B/75306B/75308B PD75312B/75316B
Mask ROM 4K/6K/8K Mask ROM 12K/16K 1024
PD75P308
One-time PROM,EPROM 8K
PD75P316
One-time PROM 16K
PD75P316A
One-time PROM,EPROM 16K
PD75P316B*1
One-time PROM 16K
512 No P30/MD0 to P33/MD3
1024
Port 4, 5 pull-up resistor incorporated LCD driving power supplying split resistor P30 to P33 NC IC
VPP
5
Electrical specifications Power supply voltage range Operating temperature range
Masked ROM products and PROM products have different current dissipation and operating temperature range *2. For details, refer to the electrical specifications of respective data sheet. 2.7 to 6.0 V -40 to +85 C * 80-pin plastic QFP (14 x 20) * 80-pin plastic QFP QFP (s 14) s * 80-pin plastic QFP (14 x 20) * 80-pin plastic TQFP (s 12) s * 80-pin plastic QFP (s 14) s * 80-pin plastic TQFP (s 12) s 2.0 to 6.0 V 2.0 to 5.5 V 5 V 5 % -10 to +70 C * 80-pin plastic QFP (14 x 20) * 80-pin ceramic WQFN (LCC with window) * 80-pin plastic QFP (14 x 20) 2.7 to 6.0 V -40 to +85 C * 80-pin plastic QFP (14 x 20) * 80-pin ceramic WQFN (LCC with window) 2.0 to 5.5 V Under investigation * 80 pin plastic QFP (s 14) s * 80 pin plastic TQFP (s 12) s
Package
5 5
*
On-chip PROM product Others
PD75P308
PD75P316 PD75P316A
PD75P316A PD75P316B
PD75P316B
----
Masked ROM products and PROM products have different noise endurance limits and noise radiation due to differing circuit scales and mask layouts.
1. The PD75P316B is under development. 2. The PD75P316A is the same as the mask ROM products.
5
Note
PROM and masked ROM have different noise endurance limits and noise radiation. When considering replacement of masked ROM products after trial manufacturing with PROM products, sufficient evaluation of CS products (not ES products) with masked ROM products should be performed.
PD75P316
PD75P316A
3. DATA MEMORY (RAM)
Fig. 3-1 shows the data memory configuration. It consists of a data area and a peripheral hardware area. The data memory consists of memory banks 0 to 3 with each bank consisting of 256 words x 4 bits. Peripheral hardware has been assigned to the area of memory bank 15. (1) Data area The data area comprises a static RAM. It is used to store program data and as a subroutine, interrupt execution stack memory. Even if the CPU operation is stopped in the standby mode, it is possible to hold the memory content for a long time by battery backup, etc. The data area is operated by memory manipulation instructions. The static RAM has been mapped to memory banks 0, 1, 2 and 3 by 256 x 4 bits each. Bank 0 has been mapped as a data area but is also available as a general register area (000H to 007H) and a stack area (000H to 0FFH) (banks 1, 2 and 3 are available only as a data area). In the static RAM, 1 address consists of 4 bits. It can be operated in units of 8 bits by 8-bit memory manipulation instructions or in bits by bit manipulation instructions, however. In an 8-bit manipulation instruction, an even address should be specified. (a) General register area The general register area can be operated either by general register operation instructions or by memory manipulation instructions. Up to eight 4-bit registers are available. That part of the 8 general registers which is not used in the program is available as a data area or a stack area. (b) Stack area The stack area is set by an instruction. It is available as a subroutine execution or interrupt service execution save area. (2) Peripheral hardware area The peripheral hardware area has been mapped to F80H to FFFH of memory bank 15. It is operated by memory manipulation instructions just as the static RAM. In the peripheral hardware, however, the operable bit unit differs from one address to another. An address to which peripheral hardware has not been assigned is inaccessible since no data memory is built in.
13
PD75P316A PD78012
Fig. 3-1 Data Memory Map
Data Memory General Register Area Stack Area 000H (8 x 4) 007H 008H 256 x 4 0FFH 100H Data Area Static RAM (1024 x 4) 256 x 4 1FFH 200H 256 x 4 2FFH 300H 256 x 4 3FFH Not On-Chip
Memory Bank
0
1
2
3
F80H Peripheral Hardware Area FFFH 128 x 4 15
14
PD75P316A
4. PROGRAM MEMORY WRITE AND VERIFY
The ROM built into the PD75P316A is a 16256 x 8-bit electrically writable one-time PROM. The table below shows the pins used to program this PROM. There is no address input; instead, a method to update the address by the clock input via the X1 pin is adopted.
Pin Name VPP
Function Voltage applecation pin for program memory write/verify (normally VDD potential). Address update clock inputs for program memory write/ verify. Inverse of X1 pin signal is input to X2 pin. Operating mode selection pins for program memory write/ verify.
X1, X2
MD0 to MD3
P40 to P43 (low-order 4 bits) 8-bit data input/output pins for progrm memory write/ P50 to P53 (high-order 4 bits) verify. Supply voltage application pin. Applies 2.7 to 6.0 V in normal operation, and 6 V for program memory write/verify.
VDD
Note
1. A lightshield cover film should be applied to the PD75P316AK provided with an erasure window, except when erasing the EPROM. 2. The one-time PROM version of PD75P316AGF is not provided with an erasure window, and therefore UV erasure is not possible.
4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES The PD75P316A assumes the program memory write/verify mode when +6 V and +12.5 V are applied respectively to the VDD and VPP pins. The table below shows the operating modes available by the MD0 to MD3 pin setting in this mode. All the remaining pins are at the VSS potential by the pull-down resistor.
Operating Mode Setting Operating Mode VPP VDD MD0 H L +12.5 V +6 V L H x: L or H L x H H H H Verify mode Program inhibit mode MD1 L H MD2 H H MD3 L H Program memory address zero-clear Write mode
15
PD75P316A PD78012
4.2 PROGRAM MEMORY WRITING PROCEDURE The program memory writing procedure is shown below. High-speed write is possible. (1) Pull down a pin which is not used to VSS via the resistor. The X1 pin is at the low level. (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) Supply 5 V to the VDD and VPP pins. 10 s wait. The program memory address 0 clear mode. Supply 6 V and 12.5 V respectively to VDD and VPP. The program inhibit mode. Write data in the 1-ms write mode. The program inhibit mode. The verify mode. If written, proceed to (10); if not written, repeat (7) to (9). (Number of times written in (7) to (9): X) x 1-ms additional write. The program inhibit mode. Update (+1) the program memory address by inputting 4 pulses to the X1 pin. Repeat (7) to (12) up to the last address.
(14) The program memory address 0 clear mode. (15) Change the VDD and VPP pins voltage to 5 V. (16) Power off. The diagram below shows the procedure of the above (2) to (12).
Repeated X Times
Write
Verify
Additional Write
Address Increment
VPP VPP VDD VDD + 1 VDD VDD
X1
P40-P43 P50-P53
Data Input
Data Output
Data Input
MD0 (P30)
MD1 (P31)
MD2 (P32)
MD3 (P33)
16
PD75P316A
4.3 PROGRAM MEMORY READING PROCEDURE The PD75P316A can read the content of the program memory in the following procedure. It reads in the verify mode. (1) (2) (3) (4) Pull down a pin which is not used to VSS via the resistor. The X1 pin is at the low level. Supply 5 V to the VDD and VPP pins. 10 s wait. The program memory address 0 clear mode.
(5) Supply 6 V and 12.5 V respectively to VDD and VPP. (6) The program inhibit mode. (7) The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at the period of inputting 4 pulses. (8) (9) (10) (11) The program inhibit mode. The program memory address 0 clear mode. Change the VDD and VPP pins voltage to 5 V. Power off.
The diagram below shows the procedure of the above (2) to (9).
VPP VPP VDD
VDD + 1 VDD VDD
X1
P40-P43 P50-P53
Data Output
Data Output
MD0 (P30)
MD1 (P31)
"L"
MD2 (P32)
MD3 (P33)
17
PD75P316A PD78012
4.4 ERASING METHOD (PD75P316AK ONLY) The content of the data programmed in the PD75P316A is erased as ultraviolet rays are irradiated to the window in the upper part. The erasable ultraviolet-ray wavelength is about 250 nm. The dose required for complete erasure is 15 W*s/cm2 (ultraviolet-ray intensity x erasure time). If a commercially available ultraviolet-ray lamp (wavelength 254 nm, intensity 12 mW/cm2) is used, it takes about 15 to 20 minutes to erase. Note 1. The content may be erased if exposed to direct sunlight or fluorescent lamp light for a long time. To protect the content, the window in the upper part should be masked with a lightshield cover film. NEC attaches such a lightshield cover film to each UV EPROM product. 2. When erasing, the distance between the ultraviolet-ray lamp and the PD75P316A should be kept normally within 2.5 cm. Remarks It may take longer to erase if the ultraviolet-ray lamp has deteriorated or if the package window is dirty and so on.
18
PD75P316A
5. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
PARAMETER Power supply voltage
SYMBOL VDD VPP VI1 VI2
TEST CONDITIONS
RATING -0.3 to +7.0 -0.3 to +13.5
UNIT V V V V V mA mA mA mA mA mA mA mA C C
Input voltage Output voltage Output current high
Except ports 4, 5 Ports 4, 5 Open-drain
-0.3 to VDD +0.3 -0.3 to +11 -0.3 to VDD +0.3
VO IOH 1 pin All pins 1 pin Peak value Effective value Peak value IOL* Total of ports 0, 2, 3, 5 Effective value Peak value Effective value
-15 -30 30 15 100 60 100 60 -40 to +85 -65 to +150
Output current low
Total of ports 4, 6, 7 Operating temperature Storage temperature Topt Tstg
*
Calculate the effective value with the formula [Effective value] = [Peak value] x duty.
CAPACITANCE (Ta = 25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance Input /output capacitance SYMBOL CIN COUT CIO f = 1 MHz Unmeasured pin returned to 0 V TEST CONDITIONS MIN. TYP. MAX. 15 15 15 UNIT pF pF pF
19
PD75P316A
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fX) *1 After VDD reaches the minimum value in the oscillation voltage range 1.0 VDD = 4.5 to 6.0 V C1 VDD X1 input frequency (fX) *1 1.0 C2 Oscillation stabilization time *2 4.19 TEST CONDITIONS MIN. 1.0 TYP. MAX. 5.0*3 UNIT MHz
X1
Ceramic resonator
X2
C1 VDD
C2
Oscillation stabilization time *2
4
ms
X1 Crystal resonator
X2
Oscillator frequency (fX) *1
5.0*3 10 30
MHz ms ms
X1 External clock
X2
5.0*3
MHz
PD74HCU04
X1 high and low level widths (tXH, tXL)
100
500
ns
*
1. Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution time. 2. Time required for oscillation to become stabilized after VDD reaches MIN. of the oscillation voltage range or after STOP mode release. 3. When the oscillator frequency is 4.19 MHz < fX 5.0 MHz, do not select PPC = 0011 as instruction execution time. If PCC = 0011 is selected, 1 machine cycle becomes less than 0.95 s, with the result that specified MIN. value 0.95 s can not be observed.
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT
PARAMETER Oscillator frequency (fXT)
TEST CONDITIONS
MIN. 32
TYP. 32.768
MAX. 35
UNIT kHz
XT1
Crystal resonator
XT2 R
VDD = 4.5 to 6.0 V Oscillation stabilization time*
1.0
2
s
C3
C4 VDD
10
s
X1 External clock
X2
XT1 input frequency (fXT)
32
100
kHz
XT1 high and low level widths (tXTH, tXTL)
5
15
s
20
PD75P316A
*
Time required for oscillation to become stabilized after VDD reaches MIN. of the oscillation voltage range or after STOP made release. When the main system clock and subsystem clock oscillation circuit are used, the area enclosed by dotted line in the figure should be wired as follows to prevent influence from the wiring capacitance, etc.. * Wiring should be as short as possible. * Do not cross other signal lines. Do not place the circuit closed to a line in which varying high current flows. * The connecting point of oscillation circuit capacitor should always be the same potential as VDD. Do not connect it to the power supply pattern in which high current flows. * Do not pick up a signal from the oscillation circuit. The subsystem clock oscillation circuit is designed to be low amplification circuit for low dissipation current, thus misoperation due to noise occurs more often than with the main system clock oscillation circuit. Therefore, when the subsystem clock is used, care is needed especially for the wiring procedure.
Note
21
PD75P316A
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (1/2)
PARAMETER
SYMBOL VIH1
TEST CONDITIONS Ports 2 and 3 Ports 0, 1, 6, 7, RESET Ports 4 and 5 X1, X2, XT1 Ports 2, 3, 4 and 5 Ports 0, 1, 6, 7, RESET X1, X2, XT1 Ports 0, 2, 3, 6, 7, BIAS VDD = 4.5 to 6.0 V IOH = -1 mA IOH = -100 A BP0 to BP7 (with 2 IOH outputs) VDD = 4.5 to 6.0 V IOH = -100 A IOH = -30 A Ports 3, 4 and 5 VDD = 4.5 to 6.0 V IOL = 15 mA VDD = 4.5 to 6.0 V IOL = 1.6 mA IOL = 400 A Open-drain pull-up resistor 1 k VDD = 4.5 to 6.0 V IOL = 100 A IOL = 50 A Open-drain
MIN. 0.7 VDD 0.8 VDD 0.7 VDD VDD -0.5 0 0 0
TYP.
MAX. VDD VDD 10 VDD 0.3 VDD 0.2 VDD 0.4
UNIT V V V V V V V
Input voltage high
VIH2 VIH3 VIH4 VIL1
Input voltage low
VIL2 VIL3
VDD -1.0
V
VOH1 Output voltage high
VDD -0.5
V
VDD -2.0
V
V0H2
VDD -1.0
V
0.4
2.0
V
Ports 0, 2, 3, 4, 5, 6 and 7 VOL1 Output voltage low SB0, 1
0.4
V V
0.5
0.2 VDD
V
1.0
V
VOL2
BP0 to BP7 (with 2 IOL outputs)
1.0 3 20
V
ILIH1 VIN = VDD Input leakage current high ILIH2
Other than below X1, X2, XT1 Ports 4 and 5 (when opendrain) Other than below X1, X2, XT1
A A A
ILIH3
VIN = 10 V
20
Input leakage current low
ILIL1 VIN = 0 V ILIL2
-3 -20
A A
22
PD75P316A
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (1/2)
PARAMETER
SYMBOL ILOH1
TEST CONDITIONS VOUT = VDD Other than below Ports 4 and 5 (when opendrain)
MIN.
TYP.
MAX. 3
UNIT
A
Output leakage current high ILOH2 VOUT = 10 V
20
A
Output leakage current low
ILOL
VOUT = 0 V
-3
A
On-chip pull-up resistor
RL1
Ports 0, 1, 2, 3, 6 and 7 (Except P00) VIN = 0 V
VDD = 5.0 V 10% VDD = 3.0 V 10%
15
40
80
k
30 2.5
300 VDD
k V
LCD drive voltage LCD output voltage deviation*1 (common) LCD output voltage deviation*1 (segment)
VLCD
VODC
IO = 5 A
VODC
IO = 5A
VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.7 V VLCD VDD VDD = 5 V 10%*4
0
0.2
V
0
0.2
V
4.5 0.9
14 3
mA mA
IDD1 4.19 MHz*3 crystal oscillation C1=C2 22 pF VDD = 3 V 10%*5 HALT mode VDD = 5V 10% VDD = 3V 10% Supply current*2 IDD3 32 kHz*6 crystal oscillation IDD4 Operating mode HALT mode VDD = 3V 10% VDD = 3V 10%
700
2100
A
IDD2
300
900
A
100
300
A
20
60
A
VDD = 5 V10% XT1 = 0 V STOP mode
0.5 0.1
20 10
A A
IDD5
VDD = 3 V10% Ta = 25C
0.1
5
A
IDD6
32 kHz crystal oscillation STOP mode
VDD = 3 V 10%*7
5
15
A
23
PD75P316A
*
1. The voltage deviation is a difference between the segment and common output ideal value (VLCDn; n = 0, 1, 2) and output voltage. 2. Current flowing in the internal pull-up resistor and LCD split resistor are not included. 3. Includes when the subsystem clock is oscillated. 4. When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode. 5. When the PCC is set to 0000 and operated in low-speed mode. 6. When operated by the subsystem clock with the system clock control register (SCC) set to 1011 and the main system clock stops. 7. When the STOP instruction is executed during the main system clock operation and the subsystem clock is oscillated.
24
PD75P316A
AC CHARACTERISTICS (Ta = -40 to +85 C , VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS Operation with main system clock tCY Operation with subsystem clock VDD = 4.5 to 6.0 V TI0 input frequency fTI 0 TI0 input high and lowlevel widths tTIH, tTIL INT0 Interrupt input high and low-level widths tINTH, INT1, 2, 4 tINTL KR0-7 RESET low-level width tRSL 10 10 10 VDD = 4.5 to 6.0 V 0.48 1.8 *2 275 kHz 114 0 122 125 1 VDD = 4.5 to 6.0 V MIN. 0.95 3.8 TYP. MAX. 64 64 UNIT
s s s
MHZ
CPU clock cycle time (minimum instruction execution time = 1 machine cycle )*1
s s s s s s
* 1.
CPU clock () cycle time is determined by oscillator frequency of the connected resonator, system clock control register (SCC) and processor clock control register (PCC). Characteristics for power supply voltage VDD vs * cycle time tCY in main system clock operation is shown below.
tCY 70 64 30 6 5 4
VS VDD (Main System Clock in Operation)
2.
It becomes 2tCY or 128/fX by interrupt mode register (IM0) setting.
Cycle Time tCY [s]
3
2
1
0.5 0 1 2 3 4 5 6
Power Supply Voltage VDD [V]
25
PD75P316A
Serial Transfer Operation 2-wire and 3-wire serial I/O mode (SCK...Internal clock output)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY1 3800 SCK high and low level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL1 tKH1 tSIK1 tKSI1 tKSO1 RL = 1 k , CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKCY1/2-50 tKCY1/2-150 150 400 250 1000 ns ns ns ns ns ns ns MIN. 1600 TYP. MAX. UNIT ns
*
RL and CL are SO output line load resistance and load capacitance, respectively.
2-wire and 3-wire serial I/O mode (SCK...External clock input)
PARAMETER SCK cycle time SYMBOL tKCY2 3200 SCK high and low level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL2 tKH2 tSIK2 tKSI2 tKSO2 RL = 1 k , CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 400 300 1000 ns ns ns ns ns ns ns TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. UNIT ns
*
RL and CL are SO output line load resistance and load capacitance, respectively.
26
PD75P316A
SBI mode (SCK...Internal clock output (master))
PARAMETER SCK cycle time
SYMBOL tKCY3
TEST CONDITIONS VDD = 4.5 to 6.0 V
MIN. 1600 3800
TYP.
MAX.
UNIT ns ns ns ns ns ns
SCK high and low level widths
SB0 and SB1 setup time (to SCK)
tKL3 tKH3 tSIK3 tKSI3 tKSO3
VDD = 4.5 to 6.0 V
tKCY3/2-50 tKCY3/2-150 150 tKCY3/2
SB0 and SB1 hold time (from SCK) SB0 and SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0 and SB1 low-level widths SB0 and SB1 high-level widths
RL = 1 k , CL = 100 pF*
VDD = 4.5 to 6.0 V
0 0
250 1000
ns ns ns ns ns ns
tKSB tSBK tSBL tSBH
tKCY3 tKCY3 tKCY3 tKCY3
*
RL and CL are SO output line load resistance and load capacitance, respectively.
SBI mode (SCK...External clock input (slave))
PARAMETER SCK cycle time SYMBOL tKCY4 3200 SCK high and low level widths
SB0 and SB1 setup time (to SCK)
TEST CONDITIONS VDD = 4.5 to 6.0 V
MIN. 800
TYP.
MAX.
UNIT ns ns ns ns ns ns
tKL4 tKH4 tSIK4 tKSI4 tKSO4
VDD = 4.5 to 6.0 V
400 1600 100 tKCY3/2
SB0 and SB1 hold time (from SCK) SB0 and SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0 and SB1 low-level widths SB0 and SB1 high-level widths
RL = 1 k , CL = 100 pF*
VDD = 4.5 to 6.0 V
0 0
300 1000
ns ns ns ns ns ns
tKSB tSBK tSBL tSBH
tKCY4 tKCY4 tKCY4 tKCY4
*
RL and CL are SO output line load resistance and load capacitance, respectively.
27
PD75P316A
AC Timing Test Points (Except X1 and XT1 Inputs)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timing
1/fX tXL tXH
X1 Input
V DD - 0.5 V 0.4 V
1/fXT tXTL tXTH
XT1 Input
VDD - 0.5 V 0.4 V
TI0 Timing
1/fT1 tTIL tTIH
TI0
28
PD75P316A
Serial Transfer Timing 3-wire serial I/O mode:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input Data
tKSO1
SO
Output Data
2-wire serial I/O mode:
tKCY2 tKL2 SCK tSIK2 tKS12 tKH2
SB0,1
tKSO2
29
PD75P316A
Serial Transfer Timing Bus release signal transfer:
tKCY3,4 tKL3,4 tKH3,4
SCK tKSB tSBL tSBH tSBK tSIK3,4 tKSI3,4
SB0,1 tKSO3,4
Command signal transfer:
tKCY3,4 tKL3,4 tKH3,4
SCK tKSB tSBK tSIK3,4
tKSI3,4
SB0,1 tKSO3,4
Interrupt Input Timing
tINTL tINTH
INT0,1,2,4 KR0-7
RESET Input Timing
tRSL
RESET
30
PD75P316A
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to +85 C)
PARAMETER Data retention power supply voltage Data retention power supply current *1 Release signal set time Oscillation stabilization wait time *2
SYMBOL VDDDR IDDDR tSREL VDDDR = 2.0 V
TEST CONDITIONS
MIN. 2.0
TYP.
MAX. 6.0
UNIT V
0.1 0
10
A s
Release by RESET tWAIT Release by interrupt request
2 /fX *3
17
ms ms
* 1. 2. 3.
Current to the internal pull-up resistor is not included. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation start. According to the setting of the basic interval timer mode register (BTM) (see below).
Wait Time BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 (Values at fXX = 4.19 MHz in parentheses) 0 1 1 1 220/fXX (approx. 250 ms) 217/fXX (approx. 31.3 ms) 215/fXX (approx. 7.82 ms) 213/fXX (approx. 1.95 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode Operating Mode
STOP Mode Data Retention Mode
VDD VDDDR STOP Instruction Execution tSREL
RESET tWAIT
31
PD75P316A
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode Operating Mode
STOP Mode Data Retention Mode VDD VDDDR STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT tSREL
DC PROGRAMMING CHARACTERISTICS (Ta = -25 to 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
PARAMETER
SYMBOL VIH1
TEST CONDITIONS Except X1, X2 X1, X2 Except X1, X2 X1, X2 VIN = VIL or VIH IOH = -1mA IOL = 1.6 mA
MIN. 0.7 VDD VDD -0.5 0 0
TYP.
MAX. VDD VDD 0.3 VDD 0.4 10
UNIT V V V V
Input voltage high VIH2 VIL1 Input voltage low VIL2 Input leakage current Output voltage high Output voltage low VDD power supply current VPP power supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH
A
V
VDD -1.0 0.4 30 30
V mA mA
Note
1. VPP including overshoot should not exceed +13.5 V. 2. VDD should be applied before VPP and should be cut after VPP.
32
PD75P316A
AC PROGRAMMING CHARACTERISTICS (Ta = 25 to 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
PARAMETER Address setup time*2 (to MD0 ) MD1 setup time (to MD0 ) Data setup time (to MD0 ) Address hold time*2 (from MD0 ) Data hold time (to MD0 ) Data output float delay time from MD0 VPP setup time (to MD3 ) VDD setup time (to MD3 ) Initial program pulse width Additional program pulse width MD1 setup time (to MD1 ) Data output delay time from MD0 MD1 hold time (from MD0 ) MD1 recovery time (from MD0 ) Program counter reset time X1 input high/low level width X1 input frequency Initial mode set time MD3 setup time (to MD1 ) MD3 hold time (from MD1 ) MD3 setup time (to MD0 ) Data output delay time from address*2 Data output hold time from address*2 MD3 hold time (from MD0 ) Data output float delay time from MD3
SYMBOL tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR
*1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR - - - - - - - tACC tOH - -
TEST CONDITIONS
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
UNIT
s s s s s
130 ns
s s
1.0 1.05 21.0 ms ms
s
1
MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125
s s s s s
4.19 2 2 2
When reading program memory When reading program memory When reading program memory When reading program memory When reading program memory
MHz
s s s s
2
2
s
ns
0 2
130
s
2
s
*
1. Symbol of the corresponding PD27C256A. 2. The internal address signal is incremented (+1) at the rising edge of the fourth X1 input. The signal is not connected to pins.
33
PD75P316A
Program Memory Write Timing
tVPS VPP VPP VDD tVDS VDD VDD + 1 VDD tXH
X1 P40 - P43 P50 -P53 tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tMOS tOPW tXL Data Input tDS tOH tDV tDF Data Output Data Input tDS tDH tAH tAS Data Input
Program Memory Read Timing
tVPS VPP VPP VDD tVDS VDD VDD + 1 VDD
tXH
X1 tXL tHAD P40 - P43 P50 -P53 tI MD0 tDV tM3HR Data Output Data Output tDFR tDAD
MD1 tPCR MD2 tM3SR MD3
34
PD75P316A
6. PACKAGE INFORMATION
80 PIN PLASTIC QFP (14x20)
A B
64 65
41 40 detail of lead end
D
C
S
80 1
25 24
F
G
H
IM
J K
P
N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
L P80GF-80-3B9-2 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 0.8 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.15 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.006 0.106 0.004 0.004 0.119 MAX.
+0.008
M
55
Q
35
PD75P316A
80 PIN CERAMIC WQFN
A B K Q
T 80
W S
D
C
U
H
I
M
1 J R
E
F
G
X80KW-80A-1 NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K Q R S T U W MILLIMETERS 20.0 0.4 19.0 13.2 14.2 0.4 1.64 2.14 4.064 MAX. 0.51 0.10 0.08 0.8 (T.P.) 1.0 0.2 C 0.5 0.8 1.1 R 3.0 12.0 0.75 0.2 INCHES 0.787+0.017 -0.016 0.748 0.520 0.559 0.016 0.065 0.084 0.160 MAX. 0.020 0.004 0.003 0.031 (T.P.) 0.039 -0.008 C 0.020 0.031 0.043 R 0.118 0.472 0.030 -0.009
+0.008 +0.009
36
PD75P316A
7. RECOMMENDED SOLDERING CONDITIONS
The PD75P316A should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document "Semiconductor Device Mount Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 7-1 Surface Mounting Type Soldering Conditions
PD75P316AGF-3B9 : 80-pin plastic QFP (14 x 20 mm)
Solderring Method Solderring Conditions Solder bath temperature: 260 C or below. , Duration: 10 sec. max. Number of times: Once, Time limit: 7 days*(thereafter 20 hours prebaking required at 125 C) Package peak temperature: 230 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Once, Time limit: 7 days*(thereafter 20 hours prebaking required at 125 C) Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or above), Number of times: Once, Time limit: 7 days* (thereafter 20 hours prebaking required at 125 C) Pin part temperature: 300 C or below , Duration: 3 sec. max. (per device side) Recommended Condition Symbol
Wave soldering
WS60-207-1
Infrared reflow
IR30-207-1
VPS
VP15-207-1
Pin part heating
---
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25 C, 65 % RH. Use more than one soldering method should be avoided (except in the case of pin part heating).
Note
For Your Information
Products to improve the recommended soldering conditions are available. (Improvements : Extension of the infrared reflow peak temperature to 235 C, doubled frequency, increased life, etc.) For further details, consult our sales personnel.
37
PD75P316A
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD75P316A.
IE-75000-R*1 IE-75001-R IE-75000-R-EM*2 Hardware EP-75308GF-R EV-9200G-80 PG-1500 PA-75P308GF PA-75P308K Software IE-control program PG-1500 controller RA75X relocatable assembler
In-circuit emulator for use with the 75X series Emulation board for use with the IE-75000-R and the IE-75001-R Emulation probe for use with the PD75P308GF 80-pin conversion socket EV-9200G-80 included PROM programmer Connect to PG-1500 with PROM programmer adapter for use with the PD75P308GF Connect to PG-1500 with PROM programmer adapter for use wtih the PD75P308K Host machine * PC-9800 series (MS-DOSTM Ver. 3.30 to Ver.5.00A *3) * IBM PC/ATTM (PC DOSTM Ver. 3.1)
*
1. Maintenance product 2. Not a built-in component in the IE-75001-R 3. Ver. 5.00/5.00A has a task swaping function, which cannot be used with this software. Refer to the 75X Series Selection Guide (IF-151) for third-party development tools.
Remarks
38
PD75P316A
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name User's Manual Instruction Application Table 75X Series Selection Guide Document Number IEM-5016 IEM-994 IF-151
Development Tools Documents
Document Name IE-75000-R/IE-75001-R User's Manual Hardware IE-75000-R-EM User's Manual EP-75308GF-R User's Manual PG-1500 User's Manual Software Operation Volume RA75X Assembler Package User's Manual Language Volume PG-1500 Controller User's Manual EEU-730 EEU-704 Document Number EEU-846 EEU-673 EEU-689 EEU-651 EEU-731
Other Documents
Document Name Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Guide Guarantee Guide Microcomputer Related Products Guide Other Other Manufacturers Volume Document Number IEI-635 IEI-1207 IEI-1209 IEM-5068 MEM-539 MEI-603 MEI-604
Note
The information in these related documents is subject to change without notice. For design purpose, etc., check if your documents are the latest ones and be sure to use the latest ones.
39
PD75P316A
40
PD75P316A
41
PD75P316A
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of MicroSoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.

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